To check the operation of SDSUII controller using an CCD4.
|
Item |
Configuration |
|
Controller |
SDSUII1 |
|
CCD |
CCD4 TK1024AB SITe1024x1024 |
|
Dewar |
D5 |
|
Focal Plane |
FP5 |
|
Cicada |
V2.1b5 |
|
Amplifier Setup |
Readout From Ampl D |
|
Initial Operating Temperature |
170K |
|
Test Instrument |
Test Box |
|
Bias Name |
Voltage (V) |
|
Video Processor Output Offset |
+4.0 |
|
Output Drain VOD |
+23.0 |
|
Reset Drain VRD |
+13.0 |
|
Output Transfer Gate VOG |
+0.5 |
|
Unused Serial |
+9.5 |
|
Unused Transfer Gate |
-5.0 |
|
Clock Name |
Voltage(V) |
|
Reset low |
+0.0 |
|
Reset high |
+10.0 |
|
Serial 1 low |
-3.0 |
|
Serial 1 high |
+9.0 |
|
Serial 2 low |
-3.0 |
|
Serial 2 high |
+9.0 |
|
Serial 3 low |
-3.0 |
|
Serial 3 high |
+9.0 |
|
Summing Well low |
-1.0 |
|
Summing Well high |
+9.0 |
|
Parallel 1 low |
-8.0 |
|
Parallel 1 high |
+5.0 |
|
Parallel 2 low |
-8.0 |
|
Parallel 2 high |
+5.0 |
|
Parallel 3 low |
-8.0 |
|
Parallel 3 high |
+5.0 |
|
Transfer Gate low |
-5.0 |
|
Transfer Gate high |
+5.0 |
|
Feature |
Value |
|
Serial Clock Mode |
STD1H1 |
|
Serial Clocking Sequence |
312 |
|
Parallel MPP Mode |
NONMPP |
|
Parallel Clock Mode |
NONMPP1 |
|
Parallel Clocking Sequence |
123 |
|
Readout Method |
Readoutmethod3 |
|
CCDI |
8us |
|
Gain |
2 |
The Gain and Noise measured at various gains CCDIs
|
Prog. Gain |
Integration time CCDI (us) |
Integration Speed |
Gain (e/ADU) |
Noise (e) |
|
2 |
8 |
Slow |
4 |
8 |
|
2 |
16 |
Slow |
2 |
5.5 |
|
4.75 |
8 |
Slow |
1.8 |
8 |
|
4.75 |
4 |
Slow |
3.7 |
11 |
Note that the CCD4 was not optimised for low noise and the purpose of the test was to verify that the DSP code was working. No waveshaping of the parallel clocks was performed and therefore spurious charge could be a major contributor to the noise.