CCD3 amplifier A stopped operating. Focal plane FP3 was rewired to enable readout from amplifiers C & D and the chip reinstalled. Amplifier C & D are to be tested.
CCD3 Site 1752x532 in dewar 3 connected to SDSUI controller running cicada V2-0b16. The dewar is connected to test box. The CCD was operated at 170K and is setup to read out from amplifiers C and D
| FVOFFSET | +1.5 | ; +1.5 Video Processor output offset |
| FVOD | +24.0 | ; +24.0 Output Drain |
| FVRD | +13.5 | ; +13.5 Reset Drain |
| FVBIAS3 | +0.1 | ; +0.0 VBIAS3 |
| FVOG | -3.5 | ; -3.5 Output Transfer Gate |
| FVBIAS5 | +0.0 | ; +0.0 VBIAS5 |
| FVABG | -7.0 | ; -7.0 VABG |
| FVBIAS6 | +0.0 | ; +0.0 VBIAS6 |
| FVABD | -7.0 | ; -7.0 VABD |
| FVBIAS7 | +0.0 | ; +0.0 VBIAS7 |
| FVS_LO | -6.0 | Serial low |
| FVS_HI | +4.0 | Serial high |
| FVP_LO | -7.8 | Parallel low |
| FVP_HI | +2.0 | Parallel high |
| FVRG_LO | +0.0 | Reset low |
| FVRG_HI | +12.0 | ; Reset high |
| FVS1_LO | FVS_LO | ; Serial 1 low |
| FVS1_HI | FVS_HI | ; Serial 1 high |
| FVS2_LO | FVS_LO | ; Serial 2 low |
| FVS2_HI | FVS_HI | ; Serial 2 high |
| FVS3_LO | FVS_LO | ; Serial 3 low |
| FVS3_HI | FVS_HI | ; Serial 3 high |
| FVSW_LO | -6.0 | Summing Well low |
| FVSW_HI | +5.0 | Summing Well high |
| FVP1_LO | FVP_LO | ; Parallel 1 low |
| FVP1_HI | FVP_HI | ; Parallel 1 high |
| FVP2_LO | FVP_LO | ; Parallel 2 low |
| FVP2_HI | FVP_HI | ; Parallel 2 high |
| FVP3_LO | -10.5 | Parallel 3 low |
| FVP3_HI | +5.5 | Parallel 3 high |
| FVTG_LO | -10.5 | Transfer Gate low |
| FVTG_HI | +5.5 | Transfer Gate high |
The parallel clocks were run in MPP mode.
The following images were taken to measure Gain and Noise.
| noise0001.fits | bias | 0 | |
| noise0002.fits | bias | 0 | |
| noise0003.fits | flat | 2 | ~ 10000 ADU |
| noise0004.fits | flat | 2 | ~ 10000 ADU |
| noise0005.fits | flat | 5 | ~ 30000 ADU |
| noise0006.fits | flat | 5 | ~ 30000 ADU |
Using IRAF script noisegain to measure noise and gain for subimage
[100:120,100:120] , at 30000ADU the gain =1.2 e/ADU and noise
= 4.0e and at 10000ADU the gain =1.2 e/ADU and noise = 3.9e
The following images were taken to measure dark current
| dark_170_0001.fits | dark | 0 | |
| dark_170_0002.fits | dark | 400 | |
| darkdiff.fits | Overscan subtracted difference image |
Using iraf script darkcurrent to measure dark current, an overscan subtracted difference image darkdiff.fits was generated and dark current calculated for subimage [70:90,210:230] as 0.13 e/sec/pixel. The difference image darkdiff.fits shows that the dark current varies over the chip peaking at ~ 0.3 e/pixel/sec at top center.
Amplifier D and the serial register appear to operate well with read noise less than 4e. However the parallel register has serious transfer problems in the second half of the image. This problem can be reduced by decreasing parallel clock 3 low voltage to < -10V and increasing parallel clock 1 & 2 low voltages to > -8V. Increasing parallel clock 1 & 2 low voltages to > -8V, increases spurious charge, creates residual image problems etc. Since the astromed 3200 does not have the capability to set different parallel clock voltages, it was decided not to continue with this chip and to try the other engineering chip. To have a look how it operated in NONMpp mode, a test image, AmpD_NonMpp.fits was taken. This image also displays a parallel transfer problem in the second half of the chip.
Amplifier C has serial smearing and quick adjustment of serial register and output amplifier voltages did not improve it. The bias, AmpC_Mpp_bias.fits and test pattern, AmpC_Mpp_test.fits images taken in MPP mode shows the same parallel lines observed with amplifier D. Due to lack of time, this amplifier was not pursued any further.