CCD2 Test Report 971030



Testing 31/10/97 04:24 AM

Aim

To improve read noise of CCD

Initial Test Setup

Tiptilt dewar cooled and on light box connected to astromed 3200 controller and using cicada to readout CCD. Shutter cable connected to control shutter. Version 1.12 of CCD2_TTT64x128 of risc code and chardware.cnf used. RISC code modified to allow the use of cicada and the shutter.

Chardware.cnf setup is as follows

DLOAD=0 # CCD output=0 / Dummy load=1 was 1

DACON=1 # Switches DACs on (=1)

SLOW=0 # Slow(=1) or fast (=0) clock rise & fall times

TC1=4.7 # Time constants for the integrator in us.

TC2=9.4

TC3=14.1

TC=2 # Time constant (1=4.7, 2=9.4, 3=14.1 us) 3

FEG=13.75 # Front End Gain (fixed by the hardware)

PGAIN=4 # Programmable gain (1, 2, 4, 8, 16) 4

CCDI=95 # Initial value of CCDI

BLKLVL=0 # Black level 0-minimum, 1-middle, 2-max

BITWT=125 # ADC Bit Weight in uV/lsb

CCDS=64

CCDP=64

#

# Bias settings in volts. min value -12.8, max value +12.7

# Except VOD: min value +2.0, max value +25.0

#

VOD=17.50 # VDDc VSSL-

VOG=-3.50 # VLGc originally specified as -6.5V by C Mackay

# GK set it at -2.5 now -3.5 for science array to have a

# workable VRSPH

VRBG=12.5 # not used

VRD=9.00 # VODc VSSL- was +9V

VABG=-4.50 # connected to unsued parallel registers

VABD=-4.50 # not used

VSSH=-4.50 # high value for flush

VSSL=-4.50 # low value for readout: normal setting

VSS=-4.50 # low value for readout: normal setting

# IDS in mA. min value 0.0, max value 2.9

IDS(uA)=1.2

#

# Clock settings in volts. min value -12.7, max value +12.8

#

VROL=-8.50 # serial low -8.5

VROH=1.50 # serial high 1.5

VRSPL=-4.50 # reset low -8.2

VRSPH=4.0 # reset high at 1.5V slope across image, set at 3.5V for

# science array. Up to 4.0 to remove image smearing

VIML=-12.50 # parallel low

VIMH=1.00 # parallel high

VSTOH=1.00 # not used

VTHERM=220.00 # regulate ccd temp to

USER=0.00 # not used - analogue output

Results

Read noise and gain for various pgain, tc, CCDI

pgain

tc

CDDI

Gain [e­/ADU]

Noise [e­]

Bias SD

4

2

95

1.264

8.9

7

4

3

95

1.85

9.6

5

8

3

95

1.02

45

42

8

2

95

0.69

52

81

2

2

95

2.58

11.1

4.5

2

3

95

3.56

11.8

3.0

4

2

190

0.614

8.5

15.0

4

3

190

0.986

7.5

7.4

8

3

190

0.509

50

100


Investigate varying reset gate lower level voltage

VRSPL

VRSPH

VROL

VROH

VOD

VRD

VOG

IDS [uA]

pgain

tc

CDDI

Gain [e­/ADU]

RN [e­]

-4.5V

+4.0V

-8.5

1.5

17.5V

9.0V

-3.5V

1.20

4

3

190

0.938

7.1

-8.5V

+4.0V

-8.5

1.5

17.5V

9.0V

-3.5V

1.20

4

3

190

0.973

8.4

-2.0V

+4.0V

-8.5

1.5

17.5V

9.0V

-3.5V

1.20

4

3

190

0.979

7.5

-2.0V

+6.0V

-8.5

1.5

17.5V

9.0V

-3.5V

1.20

4

3

190

1.011

9.09

-4.5V

+4.0V

-8.5

1.5

18.5V

9.0V

-3.5V

1.20

4

3

190

0.961

7.2

-4.5V

+4.0V

-8.5

1.5

19.5V

9.0V

-3.5V

1.20

4

3

190

0.936

8.2

-4.5V

+4.0V

-8.5

1.5

16.5V

9.0V

-3.5V

1.20

4

3

190

1.1

7.7

-4.5V

+4.0V

-8.5

1.5

15.5V

9.0V

-3.5V

1.20

4

3

190

1.019

6.8

-4.5V

+4.0V

-8.5

1.5

14.5V

9.0V

-3.5V

1.20

4

3

190

1.977

6.1

-4.5V

+4.0V

-8.5

1.5

17.5V

10V

-3.5V

1.20

4

3

190

2.0

8.4

-4.5V

+4.0V

-8.5

1.5

17.5V

8.5V

-3.5V

1.20

4

3

190

1.057

108

-4.5V

+4.0V

-8.5

1.5

17.5V

8.75V

-3.5V

1.20

4

3

190

0.991

9.1

-4.5V

+4.0V

-8.5

1.5

17.5V

8.9V

-3.5V

1.20

4

3

190

1.021

7.5

-4.5V

+4.0V

-8.5

1.5

17.5V

9.0V

-3.5V

1.20

4

3

190

1.036

7.2

-4.5V

+4.0V

-8.5

1.5

17.5V

9.1V

-3.5V

1.20

4

3

190

0.94

6.7

VRSPL

VRSPH

VROL

VROH

VOD

VRD

VOG

IDS [uA]

pgain

tc

CDDI

Gain [e­/ADU]

RN [e­]

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.20

4

3

190

0.92

6.2

-4.5V

+4.0V

-8.5

1.5

17.5V

9.3V

-3.5V

1.20

4

3

190

0.95

6.4

-4.5V

+4.0V

-8.5

1.5

17.5V

9.4V

-3.5V

1.20

4

3

190

1.05

6.5

-4.5V

+4.0V

-8.5

1.5

17.5V

9.4V

-3.5V

1.20

4

3

190

1.3

6.5

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

0.10

4

3

190

1.01

12.1

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

0.20

4

3

190

1.09

9.5

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

0.50

4

3

190

1.05

7.9

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

0.80

4

3

190

1.05

7.4

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.0

4

3

190

1.0

7.1

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

190

0.958

6.5

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.5

4

3

190

0.952

6.5

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

2.0

4

3

190

0.94

7.5

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-8.5V

1.2

4

3

190

0.99

7.0

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-6.5V

1.2

4

3

190

0.95

6.5

VRSPL

VRSPH

VROL

VROH

VOD

VRD

VOG

IDS [uA]

pgain

tc

CDDI

Gain [e­/ADU]

RN [e­]

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-5.0V

1.2

4

3

190

0.95

6.5

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

190

0.93

6.2

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.0V

1.2

4

3

190

1.00

7.1

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-2.0V

1.2

4

3

190

0.96

49

-4.5V

+4.0V

-4.5

4.0

17.5V

9.2V

-3.5V

1.2

4

3

190

0.92

6.5

-4.5V

+4.0V

-8.5

4.0

17.5V

9.2V

-3.5V

1.2

4

3

190

1.048

8.1

-4.5V

+4.0V

-8.5

2.5

17.5V

9.2V

-3.5V

1.2

4

3

190

1.04

7.2

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

190

0.96

6.7

-4.5V

+4.0V

-8.5

0.5

17.5V

9.2V

-3.5V

1.2

4

3

190

0.98

6.8

-4.5V

+4.0V

-8.5

-0.5

17.5V

9.2V

-3.5V

1.2

4

3

190

1.003

6.9

-4.5V

+4.0V

-8.5

-1.5

17.5V

9.2V

-3.5V

1.2

4

3

190

0.968

6.5

-4.5V

+4.0V

-8.5

-2.5

17.5V

9.2V

-3.5V

1.2

4

3

190

0.994

7.1

-4.5V

+4.0V

-8.5

-3.5

17.5V

9.2V

-3.5V

1.2

4

3

190

1.016

6.8

-4.5V

+4.0V

-8.5

-5.5

17.5V

9.2V

-3.5V

1.2

4

3

190

3.5

23

VRSPL

VRSPH

VROL

VROH

VOD

VRD

VOG

IDS [uA]

pgain

tc

CDDI

Gain [e­/ADU]

RN [e­]

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

190

0.998

6.9

-4.5V

+4.0V

-6.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

190

0.998

6.9

-4.5V

+4.0V

-4.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

190

1.024

6.9

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

360

0.58

15.7

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

280

0.7

9.9

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

235

0.78

6.8

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

210

0.91

7.0

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

190

0.944

6.7

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

150

1.164

7.0

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

120

1.517

8.4

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

200

0.98

6.8

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

180

1.053

7.01

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

2

190

0.614

9.4

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

2

150

0.887

8.9

VRSPL

VRSPH

VROL

VROH

VOD

VRD

VOG

IDS [uA]

pgain

tc

CDDI

Gain [e­/ADU]

RN [e­]

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

2

120

1.031

7.9

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

2

100

1.2

8.5

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

2

110

1.035

7.7

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

2

130

0.964

7.6

-3.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

190

0.986

7.0

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

190

0.918

6.4

-4.0V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

190

0.918

6.4

-5.0V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

190

1.003

7.1



The best setup seems

VRSPL

VRSPH

VROL

VROH

VOD

VRD

VOG

IDS [uA]

pgain

tc

CDDI

Gain [e­/ADU]

RN [e­]

-4.5V

+4.0V

-8.5

1.5

17.5V

9.2V

-3.5V

1.2

4

3

190

0.918

6.4

The next thing to try is to vary settling times

reset settling

serial settling

reset high time

pgain

tc

CDDI

Gain [e­/ADU]

RN [e­]

Comments

30

28

10

4

3

190

0.969

6.6

 

60

28

10

4

3

190

1.01

6.9

 

10

28

10

4

3

190

1.036

6.5

 

30

60

10

4

3

190

0.971

6.7

 

30

28

0

4

3

190

 

 

image saturates

60

28

4

4

3

190

0.92

4.5

reset high done after rdadc in readpx rather than before and reset low done at start of readpx

30

28

4

4

3

190

0.98

5.0

reset high done after rdadc in readpx rather than before and reset low done at start of readpx

60

28

4

4

3

190

0.98

4.4

reset high, resetdwell and reset low grouped together and placed after rdadc in readpx also removed serial binning in serxfer to reduce code size

60

28

4

4

3

190

0.999

4.6

reset high, resetdwell and reset low grouped together and placed before rdadc in readpx also removed serial binning in serxfer to reduce code size

60

28

11

4

3

190

0.974

7.1

reset high, resetdwell and reset low grouped together and placed before rdadc in readpx also removed serial binning in serxfer to reduce code size

60

28

2

4

3

190

1.016

4.0

reset high, resetdwell and reset low grouped together and placed before rdadc in readpx also removed serial binning in serxfer to reduce code size. Flat field has 30000 counts rather than 10000. Probably is not resetting properly.

60

28

4

4

3

190

0.971

4.4

reset high, resetdwell and reset low grouped together and placed before rdadc in readpx also removed serial binning in serxfer to reduce code size. Flat look ok. Need to try with star test pattern.

60

28

6

4

3

190

0.938

4.5

reset high, resetdwell and reset low grouped together and placed before rdadc in readpx also removed serial binning in serxfer to reduce code size

60

28

8

4

3

190

0.927

6.8

reset high, resetdwell and reset low grouped together and placed before rdadc in readpx also removed serial binning in serxfer to reduce code size

60

28

6

4

3

190

0.958

6.2

reset high, resetdwell and reset low grouped together and placed before rdadc in readpx also removed serial binning in serxfer to reduce code size. Serxfer broken up into two part. As much serial clocking is done before integrate on reset as possible and only dump charge is done for integrate on signal.

24

28

6

4

3

190

0.925

4.5

reset high, resetdwell and reset low grouped together and placed before rdadc in readpx also removed serial binning in serxfer to reduce code size

The best setup seems

reset settling

serial settling

reset high time

pgain

tc

CDDI

Gain [e­/ADU]

RN [e­]

Comments

24

28

6

4

3

190

0.925

4.5

reset high, resetdwell and reset low grouped together and placed before rdadc in readpx also removed serial binning in serxfer to reduce code size

Modified RISC code, mso-cs.h, and chardware.cnf checked into CVS as version 1.13


Testing 16-Feb-98

Aim

To get rid of first line affect by changing delays before first pixel of each line is read.

Test Setup

Checked out modified RISC code, mso-cs.h, and chardware.cnf version 1.13. Tiptilt software ran on madras at MSO. Astromed 3200 controller connected to moriarity-sso at SSO. Tiptilt dewar 2 mounted on test box with star test pattern. Environment variable ASTROMED_3200_DIR set to /priv/mephisto/mark/cicada/ccd_config/astromed_3200. Ran cicada to set its configuration information to use moriarity-sso.

Start tiptilt as follows

Results

In RISC code, mso-cs.h V1.13, changed delays in rdfullrw3 from

define(rdfullrw3, --RDFULLRW read out full serial o/p register

cffpx($1,CS)

rstccdhigh

rsthidwell

rstccdlow

delay 200

rstccdhigh

rsthidwell

rstccdlow

delay 3

rdactpx($2,CRD)

cffpx($3,CF)

)dnl


to the following

define(rdfullrw3, --RDFULLRW read out full serial o/p register

cffpx($1,CS)

rstccdhigh

rsthidwell

rstccdlow

delay 454 -- increase from 200 to 454 for extra delays

rstccdhigh

rsthidwell

rstccdlow

delay 19 -- increased from 3 to 19 for rdadc delay

rdactpx($2,CRD)

cffpx($3,CF)

)dnl

This successfully has got rid of the first line affect in subimage readout. However during operation, the line reappears, then the rdadc delay (ie delay 19) should be adjusted by a few counts.


Please send any additions and comments to:

page maintainer, mark@mso.anu.edu.au

Last Modified : Tue, 4 Nov 1997