To investigate the new chips packaged at UNSW
|
Item |
Configuration |
|
Controller |
Astromed 3200 |
|
CCD |
CCD2 |
|
Dewar |
TTT |
|
Focal Plane |
TTT |
|
Cicada |
V2.0.9 |
|
Amplifier Setup |
Left bottom |
|
Initial Operating Temperature |
255K |
|
Test Instrument |
Test Box |
|
Bias Name |
Voltage (V) |
|
Output Drain VOD |
+17.5 |
|
Reset Drain VRD |
+9.2 |
|
Output Transfer Gate VOG |
-3.5 |
|
Unused Serial |
Not used |
|
Unused Transfer Gate |
Not used |
|
VSSL,VSSH |
-4.5 |
|
Clock Name |
Voltage(V) |
|
Reset low |
-4.5 |
|
Reset high |
+4.0 |
|
VROL |
-8.5 |
|
VROH |
+4.0 |
|
VIML |
-12.5 |
|
VIMH |
1.0 |
|
VSTOH |
1.0 |
Amplifier |
Noise (e) |
Gain (e/ADU) |
Bias Slope (e) |
Comments |
Top Right
|
5.5
|
1.0
|
None
|
Excellent amplifier no blemishes
|
Bottom Left
|
5.0
|
1.0
|
None
|
Excellent amplifier no blemishes
|
|
|
|
|
|
|
|
|
|
|
|
|
Amplifier |
Noise (e) |
Gain (e/ADU) |
Bias Slope (e) |
Comments |
Bottom Left
|
5.0
|
0.9
|
None
|
Row blemishes every 17 lines starting
from row 9. Amplitude of 20ADU. -Bias, object, object-bias
|
Top Right
|
|
|
|
Image breaks
up with more light, no further tests, not cooled down
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Chip #B1 in tiptilt dewar and cooled to 217K.
Vary bias and clock voltages and integration times in order to reduce read noise.
|
VRSPL |
VRSPH |
VROL |
VROH |
VOD |
VRD |
VOG |
IDS [uA] |
pgain |
tc |
CDDI |
Gain [e/ADU] |
RN [e] |
|
-4.5V |
+4.0V |
-8.5 |
1.5 |
17.5V |
9.2V |
-3.5V |
1.2 |
4 |
3 |
190 |
1.0 |
5.0 |
|
-4.5V |
+4.0V |
-8.5 |
1.5 |
17.5V |
9.1V |
-3.5V |
1.2 |
4 |
3 |
190 |
1.0 |
4.5 |
|
-4.5V |
+4.0V |
-8.5 |
1.5 |
17.5V |
9.0V |
-3.5V |
1.2 |
4 |
3 |
190 |
1.0 |
4.7 |
|
-4.5V |
+4.0V |
-8.5 |
1.5 |
17.5V |
9.3V |
-3.5V |
1.2 |
4 |
3 |
190 |
1.1 |
5.5 |
|
-4.5V |
+4.0V |
-8.5 |
1.5 |
17.5V |
9.1V |
-3.5V |
1.1 |
4 |
3 |
190 |
0.95 |
4.5 |
|
-4.5V |
+4.0V |
-8.5 |
1.5 |
17.5V |
9.1V |
-3.5V |
1.2 |
4 |
3 |
200 |
0.95 |
4.7 |
|
-4.5V |
+4.0V |
-8.5 |
1.5 |
17.5V |
9.1V |
-3.5V |
1.2 |
4 |
3 |
180 |
1.0 |
4.7 |
|
-4.5V |
+4.0V |
-8.5 |
1.5 |
17.75V |
9.1V |
-3.5V |
1.2 |
4 |
3 |
190 |
1.0 |
4.7 |
|
-4.5V |
+4.0V |
-8.5 |
1.5 |
17.0V |
9.1V |
-3.5V |
1.2 |
4 |
3 |
190 |
1.0 |
5.1 |
The best setup in the limited time available is as follows. This gives as go performance as previous detectors
|
VRSPL |
VRSPH |
VROL |
VROH |
VOD |
VRD |
VOG |
IDS [uA] |
pgain |
tc |
CDDI |
Gain [e/ADU] |
RN [e] |
|
-4.5V |
+4.0V |
-8.5 |
1.5 |
17.5V |
9.1V |
-3.5V |
1.2 |
4 |
3 |
190 |
1.0 |
4.5 |
Chip #B1 placed in tiptilt dewar and bottom left amplifier selected. In this configuration, the chip has excellent cosmetic characteristics and the read noise of 4.5e at a gain of 1.0e/ADU. The only setting that needs to be changed from the current setup is that VRD be reduced from 9.2V to 9.1V.
.
CCD |
Amplifier |
Status |
|
CCD #B1 |
Bottom left |
Good, no bleamishes, RN 4.5e |
|
|
Bottom Right |
Not tested |
|
|
Top Left |
Not tested |
|
|
Top Right |
Good, no bleamishes, RN 4.5e |
|
CCD #B2 |
Bottom left |
Image breaks up with more light, no further tests, not cooled down |
|
|
Bottom Right |
Not tested |
|
|
Top Left |
Row blemishes every 17 lines starting from row 9. |
|
|
Top Right |
Not tested |