1 Spectrograph Detector Hardware

 

1.1 Introduction

 

The spectrograph detector hardware provides the low temperature (60-90 K), stable (±1 mK), low flexure (< 0.1 pixel per 15° change in attitude), and light-tight environment to safely mount and optimally readout the spectrograph HAWAII-2 HgCdTe PACE detector in less than 10 s with exposure times from 5 s to 7200 s. It is capable of performing standard read noise reduction sequences. The detector is to be optimised to have good quantum efficiency, sufficient well depth and linearity, while minimising read noise, dark current, drift, cross-talk, residual images, and any cosmetic problems. The detector is to be mounted in a Zero Insertion Force (ZIF) socket that is soldered into a flexi-rigid PCB Detector Mounting Board. Teflon flex circuits conduct signals from the Detector Mounting Board to hermetic subminature D connectors at the cryostat external wall. The detector is driven by a SDSU-2 Detector Controller which interfaces through a VME interface board to the Detector Controller (DC) Input/Output Controller (IOC).

 

1.2 Changes Since CoDR

 

The following decisions and changes to the baseline design have been made since CoDR:

·         PACE technology has been chosen for the HAWAII-2 HgCdTe detector. A contract to supply the detector has been signed by Gemini with Rockwell (§6.3).

·         An agreement is under negotiation between RSAA and IfA to collaborate in the design, optimisation, and characterization of the NIFS Spectrograph Detector Subsystem (§6.3).

·         The detector output amplifiers are bypassed and an external source follower J270 JFET amplifier buffers the detector multiplexer bus to eliminate amplifier glow (§6.5.5.3).

·         The detector reference output is used to reduce detector signal drift (§6.7.2). The reference output is wired the same as the signal output and the IfA Video Switch Board is used to switch between the signal and reference to enable the same video channel to sample both reference and signal.

·         The Quad Channel Coadder IR Video Board has been chosen for the SDSU-2 Detector Controller video processor, instead of two dual channel video processor boards, to maintain compatibility with the current IfA detector development system (§6.6.5).

·         The SDSU-2 Detector Controller power supply is mounted and air-cooled inside the DC thermal enclosures instead of mounted and water-cooled on the cryostat.

·         The final detector wiring will be used to characterise and optimise the detector in the test dewar as agreed at the CoDR, (§6.11.1).

 

1.3 IfA/RSAA Collaboration

 

An agreement is under negotiation between RSAA and IfA to collaborate in the design, optimization, and characterization of the NIFS Spectrograph Detector Subsystem. IfA are world leaders in developing infrared instruments using HAWAII HgCdTe detectors. IfA are at an advanced stage of developing and testing the detector system for the Air force Electro Optic System (AEOS), which uses a HAWAII-2 detector. AEOS has similar performance requirements to that of NIFS. Both are low light level spectrographs that require very low dark current, low drift, and low read noise. A substantial part of the NIFS detector system design has been adapted from the AEOS design. As the testing and characterization of the AEOS system continues over the next few months, the new ideas and concepts developed will be included into the NIFS design. On the 24 April 2002, Rockwell will deliver the NIFS science detector to IfA. RSAA and IfA will then optimize and characterize the array and further develop the NIFS spectrograph detector design as required. The science detector will then be delivered to RSAA by July 2002 for further optimizing and characterizing before being integrated with the production detector hardware and software. This will be followed by installation in NIFS.

 

1.4 Spectrograph Detector

 

NIFS is designed to use a 2048×2048 science detector. The science requirements for the instrument dictate a wavelength response from 1.0-2.5 μm and demand low dark current and low read noise performance. The higher dark currents normally inherent in detectors with sensitivity to 5 μm and the difficulty associated with blocking high thermal backgrounds at wavelengths beyond 2.5 μm further motivate the selection of a 2.5 μm cutoff device for NIFS.

 

The performance and availability of several technologies under development by Rockwell to manufacture HAWAII-2 HgCdTe detectors were investigated at the NIFS CoDR. The 2048×2048 pixel HAWAII-2 HgCdTe PACE array has been chosen because of its availability on the NIFS timescale. A contract to supply a multiplexer, an engineering grade device, and a science grade device was signed by Gemini with Rockwell on 21 September 2000. The delivery schedule is shown in Table 48. The bare multiplexer has been delivered to RSAA.

 

Table 48: Delivery Schedule For NIFS Detector.

Device

Delivery Date

Bare Multiplexer

10 February 2001

Engineering Grade

16 September 2001

Science Grade

24 April 2002

 

The performance specifications and goals agreed to in the detector contract with Rockwell are detailed in Table 49.

 

Table 49: Performance Specifications and Goals for the NIFS HAWAII-2 Detector.

Parameter

Specification

Goal

Format (pixels)

2048×2048

2048×2048

Pixel Pitch (μm)

18

18

Fill Factor (%)

90

90

Quantum Efficiency (at 77 K)

          @1.2 μm

          @ 2.3 μm

 

N/A

55%

 

70%

75%

Long wavelength cut off (μm)

2.5

2.5

Short wavelength cut on (μm)

0.9

0.9

Read noise: multiple sample (e- at 77 K)

< 15

< 5

NIFS FPA dark current (at Vb = 0.5 V)

< 1 e-/s/pix at 77 K

< 0.01 e-/s/pix at 65 K with external amplifier

Well capacity (e- at Vb = 0.5 V)

60,000

100,000

Yield (working pixels)

> 95%

> 99%

Temperature

77 K

77 K

 

In the contract, Rockwell has agreed to the following. First, in order to achieve the low dark current (0.01 e‑/s/pix) required for NIFS, it is planned to operate the detector at a lower temperature of 65 K than the normal operating temperature of 77 K. To confirm the operation of the detector at this lower temperature, Rockwell will measure the quantum efficiency of the science grade detector at 77 K and 65 K in the J, H, and K photometric bands. Second, to enable a more accurate measurement of the detector temperature, Rockwell will mount a temperature sensor on the engineering and the science chips, either on the chip carrier or an unused area of the multiplexer.

 

No mention of anti-reflection (AR) coating was made in the contract. The major reasons to have AR coating are to reduce the light piping effect of multiplexer glow through the sapphire substrate and to reduce fringing. AR coating also improves quantum efficiency by several percent. At the time the contract was signed, AR coating was still developmental and Rockwell could not provide a cost. If Rockwell develops enough confidence in applying AR coatings before the NIFS detector is manufactured, AR coating would then be considered as an upgrade option. Progress of detector development at Rockwell should be monitored to determine whether this option becomes available.

 

Additional specifications for the HAWAII-2 detector are detailed in Table 50.

 

Table 50: Additional Specification for the NIFS HAWAII-2 Detector.

Parameter

Measured Performance

Units

Architecture

4 fully independent 1024×1024 quadrants.

 

Detector Interface Circuit

SFD 0.8 μm CMOS

 

Die Size

1600

mm2

Integration Capacity

1.0×105

Carriers

Integration Capacitance

18-35

FF

Signal Conversion Gain

3.0-6.0

μV/e-

Output Signal Excursion

0.4-1.0

V

Maximum Data Rate

> 1

MHz

Maximum Settling Time

400

nsec

Power Dissipation

< 2

mW

Dynamic Range

104

V/V

 

It is currently unlikely that a 2048×2048 pixel HgCdTe/CdZnTe Molecular Beam Epitaxy (MBE) technology array will be available before NIFS is commissioned. As discussed at the NIFS CoDR, the MBE technology array has the potential to improve the performance of NIFS by achieving much lower dark current rates. There is a possibility at a future date after NIFS is commissioned that a MBE technology device will be loaned to Gemini for use by NIFS as part of the development of the NGST project. For this reason, one of the requirements for NIFS is that it is designed to be able to be upgraded to accommodate a 5 μm MBE technology device. The environmental and optical requirements to accommodate a 5 μm device are described in §5.5.4.11.1. From a detector hardware perspective, the HAWAII-2 PACE devices and HgCdTe/CdZnTe MBE devices have opposite polarity; the HAWAII-2 PACE detectors are n-on-p while the MBE detectors are p-on-n (Kozlowski et al. 1998). This can be accommodated simply by adjusting the bias and clock voltage levels. However, it is unlikely that the upgrade device will have identical packaging to the current NIFS device.

 

1.5 Spectrograph Detector Wiring

 

1.5.1 Requirements

 

The spectrograph detector wiring provides the components to safely mount the spectrograph detector and to conduct signals from the detector to the external wall of the cryostat. It also provides the mounting and wiring for the temperature sensors and heater that stabilize the detector temperature. The detector wiring should place minimal heat load on the cooling system. It should allow the detector read out time requirement of 5 s per frame to be met. It should not introduce noticeable crosstalk or read noise, and it should also be flexible enough to accommodate shrinkage during cool down.

 

1.5.2 Design Overview

 

The spectrograph detector wiring consists of two major components. The first is the Detector Mounting Board located inside the Detector Housing and the other is the flex circuits which provide the flexible wiring between the Detector Mounting Board and the hermetic connector. The Detector Housing is shown in Figure 80 and the Detector Mounting Board is shown in Figure 81. The Detector Mounting Board is a two layer, plated-through-hole, flexi-rigid PCB. The rigid part of this board is used to mount the detector ZIF socket, the wiring for the external output amplifiers, and the surface mount devices for filtering the clocks and biases. The flexible part is used to route signals to the micro-D subminature connectors that are mounted in the back of the Detector Housing. A thermally controlled copper block is soldered to the back of the Yamaichi socket to temperature stabilize the detector at 65 K to milliKelvin stability. To help achieve this milliKelvin stability, the Detector Housing is also thermally controlled at 60 K to better than 1 K stability.

 

There are two flex circuits, one for the detector outputs and biases and the other for clocks. The flex circuits run from the micro-D subminature connectors on the Detector Mounting Board to the external cryostat wall where they plug into the Ceramaseal subminature D feedthrough hermetic connectors. In doing so, they pass through several labyrinths which progressively light seal and cold clamp the flex circuits. These components are described in more detail in the following sections.

 

1.5.3 Detector Packaging Information

 

There are 128 connections to the pins of the HAWAII-2 ceramic chip carrier. These signals are listed in Appendix E (§14.1). Many of the same signals from different quadrants can be connected together so the minimum signal count can be substantially reduced below 128. The dimensions of the HAWAII-2 ceramic chip carrier are shown in Figure 91. Bonding information for the HAWAII-2 chip carrier is shown in Figure 92.

 

Figure 91: HAWAII-2 ceramic chip carrier dimensions.

 

Figure 92: HAWAII-2 bonding information.

 

 

1.5.4 Detector Housing

 

The detector, Detector Mounting Board, and the detector cooling block will be mounted inside the Detector Housing, (Figure 80). The Detector Housing is an electrically isolated light-tight (except for the image hole) box. This should guarantee that the only light the detector sees comes through the image hole in the front of the box. Electrically isolating the box from the rest of the cryostat allows the box to be electrically connected to the detector ground and act as a Faraday shield to reduce electrical noise pickup. The grounding system is discussed in §6.10.2. To help achieve the required milliKelvin stability of the detector, the temperature of the box will be servo controlled to better than 1 K at a temperature of 60 K using the secondary control loop of the Lake Shore temperature controller (§6.5.8.1). A stainless steel cold strap bolted to the side of the box cools the box. This strap connects the Detector Housing to the helium cryocooler 20 K tie point on the CWS. The detector box consists of two parts. A bottom machined from a single piece of aluminum and a lid. The Detector Mounting Board is mounted off the bottom. The only holes in the box, except for the image hole, will be holes for the electrical connectors. A light tight seal will be achieved around these connectors using quality micro-D subminature connectors with good dimensional tolerances.

 

1.5.5 Detector Mounting Board

 

The Detector Mounting Board provides the means to mount the detector together with any necessary decoupling and protection components. The PCB layout of the Detector Mounting Board is shown in Figure 93. The board is a two-layer, plated-through-hole, flexi-rigid board with the rigid part used to mount the detector socket, external amplifiers and filtering components, and the flexible part used to route signals to the connectors. A flexi-rigid board was chosen partially due to space constraints and partially due to the requirement to reduce the number of connectors and solder joints. Flexi-rigid boards have been successfully used by Manfred Meyer at ESO in their infrared cameras and by Gerry Lupinno at the IfA in the RSAA Wide Field Imager. Paul Berry at ROE is proposing to use flexi-rigid boards for their infrared wide field camera, WFCAM. In laying out the Detector Mounting Board, the following guidelines were followed. All three signal types, the outputs, biases, and clocks, were separated from each other and ground tracks placed between them. The outputs were run closest to the detector socket, then biases and then clocks. Analog ground planes were placed around and under the outputs and biases. Digital ground planes were placed under the clocks. Option jumpers were provided  to connect analog, digital, and shield grounds together, and to electrically connect shield grounds to the detector cooling block and to the Detector Housing. Option jumpers were also included to select the way the horizontal clocks (Appendix E, §14.2.1) are driven. Jumpers select whether CLKB1 and CLKB2 are driven by their own clocks or whether they are paralleled with and driven by CLK2 and CLK1, respectively. Rockwell currently recommends driving CLKB2 from the CLK1 driver and CLKB1 from the CLK2 driver. The full schematics and layout of the Detector Mounting Board are included in Vol. 2 of the CDR documentation (refer to Table 51 below for drawing numbers). The following sections discuss the detector mount, the PCB, and the selection and use of discrete components.

 

Table 51: Detector Mounting Board Drawing Numbers.

Drawing Number

Description

89-ANU-4250-3006-A3-1

Detector Mounting Board; main schematic.

89-ANU-4250-3006-A3-2

Detector Mounting Board; external output amplifier schematic.

89-ANU-4250-3006-A3-3

Detector Mounting Board; temperature control wiring schematic.

89-ANU-4250-3011-A3-4

Detector Mounting Board; PCB layout.

 

Figure 93: PCB layout of Detector Mounting Board.

 

 

1.5.5.1 Detector Mount

 

The detector is to be mounted in a Yamaichi, model number NP89-44111-G4, ZIF socket (Figure 94) to minimize the chance of damage to the detector during assembly and disassembly. The ZIF socket will be soldered onto the Detector Mounting Board. The Yamaichi socket has 21×21 pins where the HAWAII-2 ceramic chip carrier only needs 19×19 pins. A larger socket is required to allow the handle of the socket to operate freely without fouling the chip carrier. The ceramic chip carrier will be inserted into the socket such that one column of spare pins will be present on either side of the chip carrier and two rows at the top.

 

Figure 94: Yamaichi NP89-44111-G4 ZIF socket.

 

 

1.5.5.2 Detector Cooling

 

The detector ceramic chip carrier is a pin grid array of 19×19 pins with all but two signals on the two outer rows of pins (Figure 95). The inner array of 223 non-signal pins is used for thermal cooling. A hole in the Detector Mounting Board under the socket allows these cooling pins to be soldered directly to the temperature controlled copper cooling block. The mass of this copper block (approximately 80 g) has been chosen such that the expected 2 mW power dissipation of the detector over the 10 s readout burst does not increase the overall temperature of the block by more than 1 mK. The results of temperature tests to verify that this requirement can be met can be found in Appendix E (§14.7). The copper block will be soldered to the detector socket after the socket is soldered into the board. Techniques to solder this copper block to the socket have been developed and are described in Appendix E (§14.9). The temperature control system used to control the temperature of this block is described in §6.5.8. A stainless steel strip cold strap thermally connects the copper block to the inside of the Detector Housing. Silpad strips and fiberglass washers are used at the housing end to electrically isolate the block.

 

Figure 95: Pin layout of ceramic chip carrier.

 

 

1.5.5.3 External Output Amplifiers

 

The HAWAII-2 on-chip output amplifiers have similar glow problems to those of the HAWAII-1 detector, (personal communication with Klaus Hodapp). Therefore, the on-chip output amplifiers will be disabled and external amplifiers used. A description of how to disable the output amplifier and access the detector internal signal bus can be found in Appendix E (§14.2.6).

 

Two types of amplifiers have been investigated. The first uses the Texas Instrument LinCMOS TLC2272A op-amp in the same non-inverting gain configuration used by Gert Finger at ESO. The other uses a Siliconix J270 P-Channel JFET in a source follower configuration as used by Klaus Hodapp at IfA. The major performance requirements of the external amplifiers are that they have low noise (<< 10 e-), low drift (< few e-), and a settling time sufficient to allow the detector to be read out in less than 5 μs/pix.

 

Gert Finger reports that the TLC2272A op-amp contributes less than 3 e- RMS to the readout noise of a double correlated sample and the performance in gain-bandwidth (~ 2.2 MHz) is adequate for pixel times of > 5 μs. To verify its suitability, the operation and settling time of the TLC2272A op-amp configured for a non-inverting gain of three was measured and found to be very satisfactory at liquid nitrogen temperature. The drift of the TLC2272A op-amp is dominated by the input voltage drift of 2 μV/°C. This would require the temperature of the TLC2272A op-amp to be stable to a few Kelvin to achieve drift of less than a few electrons, if the output sensitivity of the detector is 3.0-6.0 μV/e- (Table 50). However, Klaus Hodapp has reported that he has performed tests on the HAWAII-2 using the TLC2272A op-amp and has concluded that the internal bus of the HAWAII-2 detector does not have the drive capability to drive the TLC2272A op-amp and therefore the output settling time is excessively long. For this reason, he recommends the use of the J270 JFET source follower that he has successfully used with HAWAII-1 detectors. We adopt this approach.

 

A schematic of the HAWAII-2 detector output circuit using the J270 JFET external amplifier is shown in Figure 96. To achieve acceptable drift, Klaus Hodapp states that the J270 will need to be temperature stabilized to 1 K. The J270s are manufactured in TO-92 plastic packages. To temperature stabilize the J270s, they will be mounted in round holes in the detector cooling block as shown in Figure 81. In order to reduce drift (see §6.7), each quadrant of the detector will have a reference as well as a signal output. We will ensure that the reference has the same drift characteristics as the signal in the following ways; 1) the reference output will use the same external amplifier circuit, 2) the signal and reference J270 JFETs for each quadrant will be electrically matched for their temperature drift performance at cryogenic temperatures, and 3) they will be mounted close together in the detector cooling block so they are tightly thermally coupled. The output impedance of the internal bus of the HAWAII-2 is high (~ 10 kΩ), so there is a potential that microphonic noise pickup from the cryocoolers could be a problem. The wiring between the detector signal and reference output pins and the gates of the J270 FET will be made mechanically rigid to reduce the likelihood of vibrational coupling.

 

Figure 96: HAWAII-2 detector output circuit.

 

 

1.5.5.4 Filtering Components

 

It will be necessary to filter the clocks and biases at the Detector Mounting Board to reduce noise. Table 52 contains a list of the capacitors selected to achieve this filtering. All capacitors are surface mount devices (SMDs) and were selected by repeated dunking in liquid nitrogen and verifying that their capacitance and dissipation did not change dramatically as they were temperature cycled. The 100 pF NPO capacitor characteristics did not change with temperature cycling as expected, while the 0.33 μF X7R and 4.7 μF Tantalum did change. The 0.33 μF X7R ceramic capacitance reduced to 0.1 μF at liquid nitrogen temperature while the 4.7 μF Tantalum reduced to 3.0 μF. However, the capacitance of both capacitors did not deteriorate any further with repeated temperature cycling and always returned to the nominal value at room temperature. As large capacitance values are only conveniently available in these capacitor types and the use of these capacitors is for filtering only, the large change in capacitance with temperature is not considered to be a problem.

 

Table 52: Capacitors Selected for Filtering on the Detector Mounting Board.

Value Required

Type Selected

Package

Usage

Comment

100 pF

100 pF NPO Nickel Barrier Ceramic

-55 to +125 C

SMD 1206

Filter all clocks

Little change in capacitance with temperature.

0.1 μF

0.33 μF X7R Nickel Barrier Ceramic

-55 to +125 C

SMD 1206

Filter all biases

Capacitance decreases to 0.1 μF at 77 K.

4.7 μF

4.7 μF Multicomp Tantalum

SMD size code B

Filter VRESET & BIASGATE

Capacitance decreases to 3.0 μF at 77 K.

 

 

1.5.6 Flex Circuits

 

Two flex circuits, one for biases and outputs and the other for clocks, are used to connect between the micro-D subminature connectors on the Detector Mounting Board and the two hermetic D connectors on the cryostat wall. The flex circuits pass through two clamps, one on the spectrograph skirt and the other at the radiation shield. The clamps provide mechanical restraint, light-tight sealing, and thermal shunting. A mechanical drawing of the flex circuits is shown in Figure 83 and Figure 84. The PCB layout of the biases and outputs flex circuit is shown in Figure 97 and the PCB layout of the clocks flex circuit is shown in Figure 98. To reduce cross talk and electrical noise pickup, ground tracks are placed between every clock, bias, and output pair. The full schematic and PCB layout of the flex circuits are included in Vol. 2 of the CDR documentation (refer to Table 53 for drawing numbers).

 

Table 53: Flex circuits drawing numbers.

Drawing Number

Description

89-ANU-4250-3011-A3-1

Clocks Flex Circuit schematic.

89-ANU-4250-3011-A3-2

Clocks Flex Circuit PCB layout.

89-ANU-4250-3013-A3-1

Biases and Outputs Flex Circuit schematic.

89-ANU-4250-3013-A3-2

Biases and Outputs Flex Circuit PCB layout.

 

 

Figure 97: PCB layout of outputs and biases flex circuit.

 

Figure 98: PCB layout of clocks flex circuit.

 

The flex circuits are to be manufactured from Taconic[1] TLE-95 132 μm (0.0052 inch) thick Teflon-based woven fabric with thin copper tracks deposited 100 μm (0.004 inch) wide with a minimum of 100 μm (0.004 inch) spacing and to a thickness of 40 μm. Only one ground connects the detector to the Detector Controller and this ground is larger than the other signals to reduce its impedance and therefore the ground noise voltage. A criss-cross ground plane of various densities is deposited on the bottom layer to provide shielding and improve cold clamping. The criss-crossing rather than solid ground planes are used to reduce thermal conductance and improve flexible. Teflon flex circuits were chosen because of their low capacitance, low dissipation factor, low dielectric constant, and low outgassing rate. A full discussion of flex circuit material choices can be found in NIFS CoDR documentation. The track widths were chosen for minimal heat flow into the cooling system through the flex circuits.

 

The connectors used at the Detector Housing end are 25 pin micro-D subminature connectors with 1.27 mm (0.050 inch) pitch from Min-E-Con[2]. The micro-D subminature connectors have proved to be reliable and are used extensively by other institutions and have been used successfully by RSAA.

 

1.5.7 Hermetic Connectors

 

Ceramaseal[3] 25 pin feedthrough subminature D connectors (Figure 99) provide the through wall vacuum seal connection to outside the cryostat. These will be welded by Ceramaseal into a RSAA-manufactured mounting flange (Figure 83 and Figure 84). A feedthrough type connector was chosen to ease assembly by allowing connectors to be plugged in from both sides of the cryostat wall. Subminature D type was chosen to simplify the manufacture and layout of the flex circuits. The connectors mating to the hermetic connectors are standard subminature D connectors.

 

 

# Pin

"A" Ref

"B" Ref

Insert
Arrangement

Part Number

25

0.529

1.804

MS18275

14442-01-W

Figure 99: Ceramaseal feedthrough subminature D connector.

 

 

1.5.8 Temperature Control

 

Due to the low drift requirement (§6.7), the detector temperature system must regulate the temperature of the detector to milliKelvin stability in the range of 60-90 K. The Lake Shore[4] Model 340 temperature controller when coupled with a Cernox CX-1080-LR temperature sensor meets this requirement. These items have been purchased. The specification and performance of this combination is described in Table 54. The Lake Shore controller will be mounted in the DC thermal enclosure.

 

Table 54: Lake Shore Model 340 Temperature Controller and Cernox Performance Data.

Sensor Type

Cernox

Temperature Coefficient

Negative

Sensor Units

Ohms

Input Range

10 ranges 10 ohm to 300 kohm

Sensor Excitation (constant Current)

10 mV max (10 current settings from 30 nA-1 mA)

Temperature Range

1.4-325 K

Standard Curve

Requires Sensor Calibration

Typical Sensor Sensitivity

-5 ohm/K at 77 K

Measurement Resolution:

0.5 mK at 77 K

Electronic accuracy:

Sensor units

Temperature Equivalence

 

±0.02%RNG±0.1%RDG

±80 mK at 77 K

Control Stability

±1 mK at 77 K

 

 

1.5.8.1 Lake Shore Model 340 Temperature Controller

 

The Lake Shore Model 340 temperature controller is a 32-bit microprocessor-based controller. It has four independent sensor inputs when purchased with the 3462 option. Two loop PID controllers with a richly featured primary loop powered to 100 W and a reduced featured lower power (1 W) secondary control loop that is intended to be used to reduce temperature gradients. In NIFS, the primary loop is used to control the temperature of the detector cooling block while the secondary loop is used to control the Detector Housing temperature. Useful features of the Model 340 include

  1. Heater Output Protection: The controller has setpoint temperature limit, heater current range limit, internal heater diagnostics, and a fuse in the heater output wiring.
  2. Setpoint ramping and zones: The setpoint ramp feature allows smooth, continuous changes in setpoint at a prescribed rate. Zones allows different PID constants to be set for different detector temperature ranges.

 

The specifications of the Model 340 and other items purchased are described in Appendix E (§14.5 and §14.6).

 

1.5.8.2 Cernox Temperature Sensor

 

The detector temperature stability requirement dictates that a CX-1080-LR Cernox temperature sensor be used for the detector cooling block. For simplicity, it was also decided to use the same type of sensor for the Detector Housing. The CX-1080 sensor is a Lake Shore Cernox™ ceramic oxynitride thin film over sapphire negative temperature coefficient resistance temperature detector. The sensors purchased were CX-1080-LR-20L. The 20L specifies that the sensor is calibrated over the temperature range 20 K to 325 K. The chosen package (SD package soldered in a LR mount) is described in Figure 100, Figure 101, Table 55, and Table 56. The LR package was chosen for ease of mounting, low thermal mass, and small size. The LR package has an SD packaged sensor mounted on a slightly more than half-rounded cylinder. This package inserts into a 3.2 mm (1/8 inch) diameter hole. Note that the solder used in this package limits the maximum upper useful temperature to 325 K.

 

Figure 100: Lake Shore SD temperature sensor package.

 

Table 55: Lake Shore SD Temperature Sensor Package.

Material of Package

Sapphire base with alumina body and lid. Molybdenum/manganese metallization on base and lid top with nickel and gold plating. Gold tin solder as hermetic lid seal.

Leads

Qty: (2) Size: 0.38 mm × 0.1 mm thick × 12.7 mm long.

Lead Material

Nickel and gold plated Kovar, uninsulated.

 

Figure 101: Lake Shore LR temperature sensor package.

 

Table 56: Lake Shore LR Temperature Sensor Package.

Material of Adaptor

Flat cylindrical copper disk, gold plated (SD soldered to adaptor).

 

 

1.5.8.3 Heater Resistor

 

In order for the temperature control system to perform to the level required, the heater resistor should have the following characteristics. First, it should be able to be located so that heat flow between the cooling power and the heater is minimized. The heater should therefore be in close thermal contact with the cooling power and if possible be mounted by the same screw that holds the cooling strap. Next, it should have low thermal resistance and thermal time lag to allow temperature control to react quickly to temperature disturbances. To meet these requirements, the detector temperature control system uses the Vishay RTO series TO-220 package resistors shown in Figure 102. This range has a low thermal resistance of 2.6 K/W. These types of resistors have been successfully used in RSAA cryostats and is the same package type used by ESO.

 

Figure 102: Vishay RTO series TO-220 package dimensions.

 

1.5.8.4 Temperature Control Tests

 

A liquid nitrogen test dewar has been set up to demonstrate the ability of the proposed temperature control system to stabilize the detector temperature to milliKelvin level at cryogenic temperatures (Appendix E, §14.7). The test system consisted of a copper block similar in size to that planned for the detector cooling block. The Cernox temperature sensor and resistor were mounted on this block and a copper braid connected the block to the 77 K liquid nitrogen cold work surface. Care was taken to make sure that all three thermal elements (sensor, heater, and cold strap) were tightly thermally coupled to reduce thermal time lags. Extreme care was also exercised with the grounding and shielding of the wiring to reduce the possibility of noise being introduced into the low level signals needed for milliKelvin level temperature control.

 

The result of temperature controlling the copper block to 150 K is shown in Figure 103. This demonstrates better than milliKelvin temperature control over a period of 4 hours. Further tests have demonstrated that this control can be maintained over days.

 

Figure 103: Temperature control of test block using the elements of the final temperature control system.

 

Additional heater resistors were added to the test setup to observe the response of the system to various disturbances such as the disturbance caused by the power dissipation in the detector during readout and disturbances of cold strap temperature variations. None of these produced significant disturbances at the test block (see Appendix E, §14.7 for the results of these tests).

 

1.6 Spectrograph Detector Controller

 

1.6.1 Requirements

 

The spectrograph Detector Controller provides the biases and the correct sequence of clocks to drive the HAWAII-2 detector. It also provides the detector output analog signal processor and the data digitizer. The Detector Controller communicates with the standard Gemini IOC to configure the Detector Controller, to initiate readouts, and to transmit command responses and image data. The Detector Controller should be able to read out the full image in less than 5 s, and be able to expose the detector from 10 s to 7200 s. It should be capable of performing standard read noise reduction sequences.

 

1.6.2 Design Overview

 

The block diagram of the design of the spectrograph Detector Controller is shown in Figure 104.

 

Figure 104: Block diagram of spectrograph Detector Controller.

 

The design of the spectrograph Detector Controller consists of the following:

 

1.        San Diego State University SDSU-2 Detector Controller configured with the following components:

·         Quad Channel Coadder IR Video Board configured for HAWAII-2 detector. This board provides the capability to readout the detector through four video processing channels.

·         IR Clock Driver Board, which provides 24 clock drivers. The clock drivers will drive the detector multiplexer clocks, the detector bias supplies, and the control signal and video offset voltage for the Video Switch Board.

·         Fiber Optic Timing Board, which provides the timing sequencer and the communication hub for the other boards.

·         Two core fiber optic communication cables. Three meter length that runs from the Timing Board to the IOC input/output connection panel and two meter length that runs from the IOC controller connection panel to the VME Interface Board.

·         Power Controller, 6 slot backplane, and enclosed housing.

2.        Video Switch Board that plugs into the SDSU-2 Controller Housing. This board is to be provided by IfA. The Video Switch Board will enable the analog inputs of the Quad Channel Coadder IR Video Board to be switched between signal and reference in order to reduce signal drift.

3.        SDSU-2 VME Interface Board that plugs into the DC IOC. This board provides the fiber optic communication interface between the SDSU-2 controller and the DC IOC.

4.        IOC input/output connection panel with two fiber optic feedthroughs and a power supply feedthrough connector. Details of the power supply feedthrough connector will be obtained from Bob Leach. This panel provides a reliable place to connect and disconnect the fiber cables from the VME Interface Board.

5.        Air cooled SDSU-2 power supply for 6 slot system with special cable to go through IOC input/output connection panel. The power supply will be mounted inside the DC thermal enclosure. The cable lengths are as follows. Three meter length that runs from the SDSU-2 controller to the IOC input/output connection panel and two meter length that runs from the connection panel to the power supply.

6.        External cryostat wiring manufactured from a composite of cables and wires. This wiring provides the connection from the hermetic connector of the NIFS cryostat to the SDSU-2 controller boards.

7.        Water jacket and hoses for cooling the SDSU-2 Controller Housing.

 

The SDSU-2 Controller Housing is bolted to the cryostat adjacent to the detector hermetic connector as shown in Figure 58 and is water cooled by bolting a RSAA standard water jacket to the housing.

 

1.6.3 San Diego State University SDSU-2 Detector Controller

 

The San Diego State University SDSU-2 Detector Controller was chosen for the following reasons: Gemini has adopted SDSU-2 controllers as their standard controller. The SDSU-2 controllers can be easily interfaced to the VME-based Gemini Standard IOC. SDSU controllers have been in use at RSAA for several years and have been used in several instruments.

 

1.6.4 SDSU-2 Detector Controller Thermal Protection

 

The SDSU-2 Controller Housing is to be water-cooled and the power supply is to be air-cooled. If the water-cooling fails, then the controller housing electronics may overheat. The SDSU-2 Detector Controller has thermal cutout switches for both the electronics in the housing and the power supply. The thermal switches disable the ±6.5 V, ±16.5 V, and ±36 V supplies at the power control board if the temperature rises above 50 C. This powers down all electronics inside the controller except for the +5 V supplies to the Digital Signal Processors (DSPs) and thus substantially reduces the power dissipation in both the housing and the power supply. Once the controller has cooled down and the thermal switches reset, the timing board “power on” command can be used to re-enable these supplies. The power supply is mounted inside the DC thermal enclosure. The DC thermal enclosure is water-cooled and has a thermal cutout switch if the water-cooling fails and the temperature gets too high.

 

1.6.5 SDSU-2 Video Processor Board

 

There are two different video boards available for use with the SDSU-2 controller. The two boards are the Dual Channel IR Video Board and the Quad Channel Coadder IR Video Board. A comparison of these two boards was made at the NIFS CoDR. Both boards have essentially identical analog video processing chains. The Dual Channel IR Video Board has the capability of two analog video processing chains while the Quad Channel Coadder IR Video Board has four. Apart from the different number of video channels, the major difference between the two boards is that the dual video board provides six biases while the coadder board provides image-processing capability by the Motorola DSP56002 DSP and 1 Mword of SRAM. The Quad Channel Coadder IR Video Board solution was chosen so as to be compatible with the IfA system, even though the DSP image-processing capability will not be used. IfA are doing their AEOS development work with this system and it will be used to do the characterisation and optimisation of the NIFS science detector. The DSP code which IfA develops should therefore run with only minor changes on the NIFS system. All detector biases will need to be provided by the SDSU-2 Clock Board.

 

It is normal practice to customise the input stages of the IR video boards to suit the way in which they are used. Appendix E (§14.10.1) details the required coadder video board modifications. The schematic of the modified board is included in Vol. 2 of the CDR documentation (Drawing 89-ANU-4250-3020-A3). As there is no gain in the J270 external output amplifier or the Video Switch Board, the full gain of ×24 must be provided by the first (×2) and second (×12) stage of the coadder board video chains. The inputs of the coadder board video chains are configured as differential amplifiers. The detector signals are fed into the inverting inputs and offset signals (§6.6.7) are fed into the non-inverting inputs .

 

1.6.6 SDSU-2 IR Clock Driver Board

 

The IR Clock Driver Board is a standard SDSU-2 IR clock board except that the clock drivers (normally Analog Devices AD829) of clocks 0-3 have been replaced with faster rise time devices (Analog Devices AD811). This was necessary because the detector horizontal register clocks (CLK1, CLK2, CLKB1, and CLKB2) require faster rise times than the AD829 drivers can provide. Appendix E (§14.10.2) details the IR clock driver board modifications. The schematic of the modified board is included in Vol. 2 of the CDR documentation (Drawing 89-ANU-4250-3021-A3).

 

1.6.7 IfA Video Switch Board

 

The Video Switch Board switches the input of the Quad Channel Coadder Video Board between the detector signal outputs and the detector reference outputs. One of the clocks from the IR Clock Driver Board controls the switching (§6.7.2). The schematic and layout of the Video Switch Board can be found in Vol. 2 of the CDR documentation (Drawings 89-ANU-4250-3022-A3-1 and 89-ANU-4250-3022-A3-2). The Video Switch Board consists of two Harris HI-303 quad analog switch integrated circuits. Each integrated circuit has two sets of complimentary analog switches that enable the outputs to be switched between the detector signal and reference. The analog switch control comes in through connector J4. The 10 kΩ source resistors of the detector external output amplifiers are located on this board before the analog switches (Figure 96). Positioning these resistors before the switch will enable a stable source current to each JFET amplifier thereby reducing signal settling times and eliminating variations in power dissipation if the source resistors were switched. To enable fast subtraction of the offset difference between the signals and the references, one of the clocks is routed through this board and is fed to the non-inverting inputs of the differential amplifiers of the coadder board. This clock is switched at the same time as the signal input. The low voltage level of this clock will be set to the signal offset and the high voltage level set to the reference offset.

 

1.6.8 SDSU-2 Detector Controller Performance

 

Table 57 summarizes the SDSU-2 Detector Controller characteristics.

 

Table 57: SDSU-2 Detector Controller Performance.

Parameter

Description

 

 

Power Dissipation

4 channel system : Controller Housing ~ 50 Watts, Power Supply ~ 50 Watts.

Fiber Optic Cable

AT&T ST type connectors, 62.5/125 micron multimode Ge-doped silica core fiber cable. To stop light leaks, outer sheath must be black. 

Command and Reply Transmission

32 bit long, plus one start bit, with the most significant bits first, NRZ scrambled. Twenty-four bits contain useful data, and eight are header bits. Commands are transmitted at 4 Mbits/s and replies are received at 50 Mbits/s.

Data Transmission

Image data word is 16 bits plus 1 start bit, Fiber rate is 50 Mbits/s, Pixel transmission time is 400 ns/pixel with 60 ns buffer between pixels, data rate is 2.5 Mpixels/s.

Timing Sequencer

Motorola DSP560002 40 ns per instruction time, 50 MHz clock.

Timing Sequencer Memory

32K´24bits; 8K P: program, 8K X: data, 16K Y: data memory.

Clock Driver Board

24 drivers per board, with selectable voltage range of each 0 to +5 V, -5 V to 0 V and –5 V to +5 V. The level within these ranges is set by 12 bit DACs.

A/D converter

Datel ADS-937, 16 bit straight binary, 1 μs conversion time (1 MHz sampling rate) including 300 ns internal sample/hold.

 

The specification for the non-destructive read (NDR) readout time of the whole detector is 5 s. The HAWAII-2 has 2048×2048 pixels and will be read out through four amplifiers. This requires a pixel rate of ~ 5 μs/pixel. For a four video channel SDSU-2 controller, the fiber optic communication link limits the pixel rate to a minimum of 1.6 μs/pixel (4/2.5 Mpixels/s data rate). This more than satisfies the required pixel rate. The timing sequencer has a clocking time resolution of 40 ns and the analog-to-digital converter on the Quad Channel Coadder Video Processor Board has a 1 μs conversion time including the time for the 300 ns internal sample/hold. These times also more than satisfy the required pixel rate.

 

The timing board DSP will not be required to store any pixel data. Therefore from past experience and from looking at HAWAII DSP code from other groups, the timing sequencer memory of 32K×24bits (8K P: program, 8K X: data, 16K Y: data memory) is more than adequate.

 

The IR Clock Driver board can drive up to 24 clocks or biases. Each has a selectable voltage range of 0 V to +5 V, -5 V to 0 V, and -5 V to +5 V. This range is more than adequate if the clocks and biases of each quadrant of the HAWAII-2 detector are connected together so each quadrant requires 10 clocks and 5 biases. The selectable voltage ranges will allow both the HAWAII-2 PACE device (n-on-p) (§6.4) or the HgCdTe/CdZnTe MBE device (p-on-n) (§6.4) to be accommodated.

 

The HAWAII-2 has a usable dynamic range of 1.0×105 and the predicted read noise is 5 e- (Table 49). A 16 bit A/D converter is then adequate to digitise the analog signal.

 

1.6.9 SDSU-2 Controller External Cryostat Wiring

 

SDSU-2 controller external cryostat wiring is the wiring between the hermetic connector and the SDSU-2 controller boards. The schematic of the external cryostat wiring is included in Vol.2 of the CDR documentation (Drawing 89-ANU-4250-3014-A3). The wiring will be manufactured from a composite of cables and wires that have low capacitance to reduce settling times.

 

1.7 Detector System Bias Stability

 

1.7.1 Requirement

 

High levels of bias stability are essential for the detector system because of the long integration times planned (3600 s), the low readout noise (few e-) expected, and the way the readout will be performed. This is especially true if the fixed pattern dark current discussed at the NIFS CoDR is to be accurately subtracted. The specification for bias stability is that the drift over the longest exposure time should be less than the read noise. The stability of the SDSU-2 controller driving a HAWAII-2 detector has been highlighted as an issue that needs careful consideration (Klaus Hodapp, priv. comm.). To address detector drift problems, Rockwell has built a reference circuit onto the HAWAII-2 detector that should to be able to be used to reduce drift. The planned use of this reference circuit together with other issues associated with drift are discussed in the following sections.

 

1.7.2 HAWAII-2 Reference Circuit

 

As discussed at the NIFS CoDR, the output of the HAWAII-2 is likely to be highly temperature dependent. To achieve the drift requirement, it will be necessary to control the temperature of detector to the milliKelvin level. A detector temperature control system has been designed to achieve this requirement and has been discussed in §6.5.8. However, due to self-heating of the detector near the output amplifier or the regions near the multiplexer shift register and the finite thermal resistance between the detector cooling block and the detector, it is unlikely that the desired temperature control of the detector itself will be achieved. For this reason, the reference output on the detector will be used to subtract residual drift from the signal.

 

The reference circuit provided by Rockwell on the detector is shown Figure 105. The reference output is enabled after each row is read out, i.e., on the 1025th horizontal clock cycle. The reference circuit is similar to the signal circuit except that the gate of the source follower is connected to Vreset instead of the unit cell and there is no capability to bypass the internal output amplifier. Rockwell has stated that as the reference output amplifier is only enabled for a very short period of time, it does not introduce appreciable glow.

 

To maintain similar drift characteristics on both the signal and reference, both signal and reference video processing circuits are made as similar as possible. To this end, identical external output amplifier circuits are used as described in §6.5.5.3 with matched J270 FETs mounted together in close thermal contact. The wiring of the signal and reference are routed alongside each other. The signal and reference are fed into the same analog video channel by utilizing a video switcher before the SDSU-2 analog board to switch between the signal and reference (§6.6.7). The Video Switch Board switches from the signal to the reference on the 1025th horizontal clock cycle and 32 samples of the reference are taken. The reference samples can then be used in a similar manner as the overscan in CCD images and be averaged and subtracted from the image area. By averaging the 32 samples, the noise introduced by the reference becomes insignificant.

 

Figure 105: HAWAII-2 reference circuit.

 

 

1.7.3 SDSU-2 Controller Stability

 

The HAWAII-2 detector will have a read noise < 5 e- with multiple sampling (Table 49) and a signal conversion gain of 3.0-6.0 μV/e- (Table 50). If this read noise is realized, the bias stability requirement demands that drift be maintained below 15-30 μV at the input to the video processor board.

 

The drift characteristics of devices used in the video chain and in the generation of biases and clocks are show in Table 58.

 

Table 58: Drift of devices used in the video chain and in the generation of biases and clocks.

Device

             

Grade

Description

Usage

Drift with temperature

Drift with temperature referenced to input (μV/K)

Current Drift (nA/K)

AD829

JN

Video Input amplifier

Video Chain

0.3 μV/K (typ)

0.3 (typ)

0.5

ADS-937

-

Video ADC

Video Chain

30 ppm/K (typ)

10 (typ)

 

OP270

G

Reference buffer op-amp

Video Offset, Biases, and Clocks

0.7/3.0 μV/K (typ/max)

0.7/3.0 (typ/max)

0.02

AD586

MN

Reference

Video Offset, Biases, and Clocks

2 ppm/K (max)

10 (max)

-

DG405A

DY

Analog switch

Biases and Clocks

 

 

 

OP470

G

Bias buffer op-amp

Video Offset

2.0 μV/K (typ)

2.0 (typ)

0.06

DAC8420

F

Bias DAC

Video Offset, Biases, and Clocks

4 ppm/K (typ)

20 (typ)

-

 

Table 58 shows that the video chain drift is limited by the ADS-937 video ADC at 10 μV/K and the biases and clocks are limited by the DAC8420 at 20 μV/K. As there are no better grades for these two devices, there is no reason to upgrade other devices on the boards.

 

The above drift data indicate that the controller must be temperature stabilized to a few degrees over the time of the longest exposure ( 2 hr) to achieve the drift requirement. In practise, this requirement can be relaxed slightly because the reference circuit will compensate for some drift (§6.7.2). The SDSU-2 controller will be water-cooled (as discussed at the NIFS CoDR) so its temperature will depend primarily on the water temperature. The Gemini water chiller temperature is specified to track the dome temperature. An indication of the electronics temperature variation of a water-cooled SDSU-2 controller can been obtained by inspecting the temperature log files of the RSAA Wide Field Imager (WFI) which uses water-cooled SDSU-2 controllers (Figure 106). The WFI water chiller uses an on-off thermostat with a hysteresis of 2 K so it is not as well regulated as the Gemini water chiller. Figure 106 shows that the WFI utility board temperature varies by only 2 K over a period of two days with periods of many hours when the temperature varies by < 0.5 K. Unfortunately, there are no corresponding records of dome temperature. These data and the above discussion suggest that the NIFS detector controller will have acceptable drift characteristics if the temperature of the Gemini water chiller varies slowly (< 2 K/hr) in response to changes in dome temperature.

 

Figure 106: Likely temperature variation of SDSU-2 controller.

 

 

1.8 Readout Methods

 

The performance of the NIFS detector can be improved by proper selection of the readout method. NIFS implements three readout methods; double correlated sampling (DCS), Fowler sampling (Fowler & Gatley 1990), and linear fitting. Garnett & Forrest (1993) provide a full analysis of the three sampling schemes for different observing situations. Fowler sampling and linear fitting are superior to DCS in read noise limited situations (assuming that the read noise is dominated by white noise). Both provide ~ Önsamples improvement over DCS. Fowler sampling performance is a function of its duty cycle, which is the ratio of time spent sampling to the total observing time. Fowler sampling achieves its best performance at a duty cycle of 2/3, i.e., sampling the “pedestal” and “signal” level each for 1/3 of the total observing time. At this optimum duty cycle, Fowler sampling is approximately 6% inferior to linear fitting. In the background-limited case, the best theoretical signal-to-noise ratio is achieved with DCS.

 

1.8.1 Double Correlated Sampling

 

In the DCS method, the detector is reset several times, the start pixel value is read once, charge is accumulated for the exposure time, then the end pixel value is read once. The end pixel value is then subtracted from the start pixel value. This method is the fastest readout method. It is a useful method for idle mode as it removes most of the bias structure. It is also the preferred method for observing bright objects with NIFS.

 

1.8.2 Fowler Sampling

 

In Fowler sampling (Figure 107), the detector is reset, the start pixel value is repeatedly read out n/2 times while these values are co-added on a pixel-by-pixel basis and stored, charge is accumulated for the exposure time after which the end pixel value is repeatedly read out n/2 times while the values are co-added on a pixel-by-pixel basis. The co-added results from before and after the exposure are subtracted and normalized.

 

For read noise limited performance, the improvement in signal-to-noise ratio of Fowler sampling over that of the DCS method is

where η is the duty cycle of Fowler sampling such that η=n/nmax, nmax is the maximum number of samples possible for a given exposure time, and n is the number of samples. This equation has a maximum when η = 2/3 for a given nmax. For exposure times Tint >> nTread , the improvement in signal-to-noise ratio is

Consequently, Fowler sampling is the preferred readout method for medium length NIFS exposures.

 

Figure 107: Fowler sampling. Nondestructive readouts are concentrated at the beginning and end of the integration ramp.

 

 

1.8.3 Linear Fitting

 

In the linear fitting method (Figure 108), the detector is reset, the pixel values are repeatedly read at equal periods through the exposure time. The series of NDRs are saved. After each NDR, the accumulated data set is linearized and a least-squares linear regression is fitted through the NDRs to define the incident photon rate. This method has a number of advantages. The bias is very small, so that in real time you see useful data without needing a previous dark exposure. Long exposures are punctuated by frequent displays so that one can see how the exposure is progressing. And pixels that saturate (as on bright stars) are still correctly measured by using only the span of NDRs up to saturation. For read noise limited performance, the improvement in signal-to-noise ratio over that of the double correlated sample method is

where n is the number of reads. Linear fitting is the preferred readout method for long exposures with NIFS.

 

Figure 108: Linear fitting. Nondestructive readouts occur at equal intervals along the integration ramp.

 

 

1.8.4 Multiplexer Glow

 

Multiple sampling schemes are complicated by multiplexer glow (Figure 109). Multiplexer glow is light emitted by on-chip components within the multiplexer circuitry whenever the multiplexer is clocked. This is distinct from on-chip amplifier glow which is eliminated by using external amplifiers (§6.5.5.3). Multiplexer glow can only be reduced by AR coating the detector during manufacture (§6.4). This reduces the light piping effect of the glow through the sapphire substrate. Due to multiplexer glow, there is a trade-off between the number of NDRs and the reduction in system noise. As the number of samples increases the read noise decreases, but a point is reached where the system noise increases due to the dominance shot noise from the multiplexer glow dominates the noise. This is shown in Figure 110 where various noise sources are plotted for a subimage at the center of the array far from the multiplexer glow sources. The increasing curve in Figure 110 shows the contribution to the noise from shot noise. The decreasing curve shows the expected improvement in read noise from linear fitting. The parabolic curve shows the addition of these two noise sources. The number of samples before the system noise increases is detector dependent. For the HAWAII-1 detector in Figure 110, this number is 64. The HAWAII-2 multiplexer is supposed to have improvements to reduce this glow (Appendix E, §14.2.1), but the extent of this improvement is unknown at present.

 

Figure 109: Multiplexer glow of a HAWAII-1 array with glow centers in the top and bottom right corners and in the center of top and bottom edges (Finger et al. 2000).

 

Figure 110: Read noise as a function of integration time for continuous multiple nondestructive sampling of HAWAII-1 at sample rate of one sample per second (Finger et al. 2000).

 

To overcome this limitation, the capability to digitally filter each pixel is provided. Digital filtering is the averaging of multiple ADC conversions sampling the video signal of each individual pixel in the time interval during which that pixel is addressed. Digital filtering enables the equivalent of a large number of NDRs to be recorded while clocking the multiplexer fewer times. Since external output amplifiers are used, no additional glow is generated by slowing down the frame rate and increasing the pixel time to perform this multiple sampling per pixel. The read noise should improve as the square root of the number of multiple samples. Digital filtering will be implemented in all three readout methods.

 

1.9 DSP Code

 

The SDSU-2 Detector Controller has three DSPs. One is on the VME Interface Board to the IOC controller, the second is on the Timing Board, and the third is on the Quad Channel Coadder IR Video Board. Code is required for these three DSPs. The following sections discuss this code.

 

1.9.1 VME Interface Board

 

The VME Interface Board provides the communication path between the fiber link on the Timing Board and the DC IOC. It send commands from the IOC to the Timing Board and accepts image data from the Timing Board and writes them to the VME memory using an on-board DMA (Direct Memory Access) controller. The VME Interface Board utilizes a Motorola 56001 DSP for housekeeping and DMA address generation. A local buffer memory (32K´24bits) stores incoming image data to avoid lost data if the VMEbus is unavailable for short periods. Interrupts can be generated by the VME Interface Board, and VMEbus memory can be written to or read from under control of the on-board DSP. The DSP has the capability to perform some limited data processing. However, no special data processing or data sorting is required for NIFS. The SDSU-2 VME Bus Interface Board Users Manual describes the board, the DSP code, and the command interface.

 

In all three readout methods discussed above (§6.8), a single command will be issued from the DC IOC to the Timing Board to initiate readouts. In response to this command two or more frames of image data will be transmitted to the DC IOC for data processing and storage. In the case of linear fitting, the frames are transmitted at regular intervals throughout the exposure. A method of synchronizing the data transfer must be provided in order to begin early processing of these data before the exposure is complete and to display the image building up during the exposure. It is proposed to set up the VME Interface Board to generate interrupts at regular intervals and between frames of data (§8.7.4.1.3) to achieve this data synchronization. The standard VME Interface Board DSP code does not implement this capability. However, NOAO have code for GMOS that does. The GMOS code is designed to operate with a single output CCD and may require minor modifications to better suit our application.

 

1.9.2 Timing Board and Quad Channel Coadder IR Video Board

 

The Timing Board and Quad Channel Coadder IR Video Board DSP code (herein called timing board DSP code) is the major piece of software that drives the SDSU-2 Detector Controller. It is responsible for controlling all aspects of reading out the detector and the setting and turning on and off of the clock and bias voltages.

 

A preliminary draft of the command interface between the SDSU-2 Detector Controller timing board DSP code and the software running on the DC IOC has been defined. This command interface has the ability to set the bias and clock voltages, set exposure times from 10 s to 7200 s, and provides the necessary commands to implement the required readout methods (§6.8). It provides an abort command to abort both an exposure and any other commands that do not finish execution within an acceptable short period of time. It also provides commands to turn the bias and clock voltages on and off in the correct sequence. As agreed at the NIFS CoDR, no capability to read a region of interest will be provided. A description of the HAWAII-2 detector with respect to the biases, the clocks, and the sequencing of clocks to readout the detector can be found in Appendix E (§14.2).

 

The DSP code will be developed in collaboration with IfA. At an appropriate time after IfA have tested their Video Switch Board, a copy of the IfA DSP code will be obtained and modified as required to operate with the NIFS DC IOC software.

 

In writing the DSP code, the following rules will be followed. To minimize down time, all code will be thoroughly tested and debugged. Where exceptions or faults occur, the exception or fault will be reported. However, corrective action to minimize the impact on the continuation of observing will be taken except in circumstances where there is a possibility of damage to the detector.

 

1.10 Wiring Considerations and Grounding

 

1.10.1 Grounding And EMI Shielding

 

It is very important to properly design the grounding and shielding to obtain reliable operation and the best noise performance. As far as possible the following rules have been adhered to:

 

1.        Shielded coax or twisted pair cable have been used to interconnect components. The shields of these cables are only connected at one end to avoid ground loops.

2.        Electrically noisy components and signals are kept away from low level sensitive ones and ground shields are placed in between. The SDSU-2 Detector Controller will be mounted on the cryostat and kept away from the noisy DC IOC which will be mounted in one of the thermal enclosures and the Components Controller electronics and IOC which will be mounted in the other thermal enclosure.

3.        Noisy grounds are kept separate from low level electronics grounds. Several grounds are used and these are connected at one star point. The first ground will be a hardware ground used for mechanical enclosures, chassis, racks, and so on. The second will be a noisy ground used for relays and motors. The third will be a digital ground, and the last will be an analog ground. The AC power ground will be connected to the hardware ground.

 

1.10.2 Detector Grounding Scheme

 

Figure 111 shows the proposed detector ground system. Close attention has been paid to the detector grounding and shielding to achieve the required low noise performance of the detector. The NIFS cryostat forms the primary shield around the detector. It is not practical to completely electrically isolate the cryostat from the telescope and mains grounds, and ground the cryostat only through the SDSU-2 Detector Controller. This is because of the physical size and weight of NIFS and its low flexure requirement. Instead, the cryostat will be grounded to the telescope. The telescope ground is reported to be a noisy ground so is not ideal for detector grounding purposes. Consequently, NIFS will also use an internal detector shield which is insulated from the cryostat. Ideally, this internal shield would completely enclose the detector, the Detector Mounting Board, and the cryostat wiring and be connected to the Detector Controller ground.

 

The internal shield will be implemented by mounting the detector inside the Detector Housing, electrically insulating the Detector Housing from its surroundings as described in §6.5.4, and connecting it electrically to detector ground. The cryostat wiring is shielded by running ground tracks between each signal and placing ground planes on the bottom of the flex circuits as described in §6.5.6. The detector controller grounding scheme (Figure 111) is based on making the video board the star point and from it to have short ground wires to the clock board, the controller chassis, and detector ground. The star point is ultimately attached to Gemini’s quiet instrument ground (Mark Hunten, priv. comm.). The detailed schematic of the detector ground wiring is included in Vol. 2 of the CDR documentation (Drawing 89-ANU-4250-3005-A3).

 

Figure 112 shows the proposed Components Controller ground system. Care has been taken so that motors, encoders, cryocooler lines, drives, cables, and mechanical couplings do not ground the cryostat and cause multiple ground loops through the instrument.

 

The cryocooler radiates a strong magnetic field. The intensity and extent of this magnetic field will be measured when the cryocoolers arrive. The Detector Controller, Detector Mounting Board, and cryostat wiring will be kept out of this field as much as possible. Otherwise, magnetic shielding of these components will be required. The radiation from the cryocooler is directional so care will be exercised when orienting the cyrocooler head with respect to the Detector Controller. The SDSU-2 Detector Controller is housed in a sealed aluminium box and therefore has good electrical (but not necessary good magnetic) shielding. Noisy cables (e.g., Components Controller cables) are routed so that they are as far as practical away from the Detector Controller. Local motors are powered down when not driving. Motor leads are shielded and the shields are broken at the cryostat wall.

 

Figure 111: Detector ground system.